A Compression Router for Low-Latency Network-on-Chip

Network-on-Chips (NoCs) are important components for scalable many-core processors. Because the performance of parallel applications is usually sensitive to latency NoCs, reducing it a primary requirement. In this study, compression router that hides (de)compression-operation delay proposed. The (de)compresses contents incoming packet before switch arbitration completed, thus shortening length without penalty and network injection-and-ejection latency. Evaluation results show improves up 33% application (conjugate gradients (CG), fast Fourier transform (FT), integer sort (IS), traveling salesman problem (TSP)) 63% effective throughput by 1.8 ratio on NoC. cost an increase in area its energy consumption 0.22mm2 1.6 times compared conventional virtual-channel router. Another finding off-loading decompressor onto interface decreases compression-router 57% at expense moderate communication